As shown by FIG. 1, host equipment 10 such as a personal computer, a work station or the like, typically includes a central processor unit ("CPU") 20 and memory 30. Signals to and from host 10 are communicated via one or more ports, such as port 40. A cable 50 is coupled between host 10 and one or more peripheral devices 60 (e.g., a printer) through a port 70 on the device. Cable 50 has a first connector 80 that mates with a connector on the host port 40, and has a second connector 90 that mates with a connector on the peripheral port 70. For ease of illustration, cable connectors 80 and 90 are shown spaced-apart from their mating connectors on host 10 and peripheral 60, respectively. In practice, connector 80 mates with connector 40, and connector 90 mates with connector 70.
Port 40 will typically be governed by an industry-accepted standard that defines port connector pin-out, signal functions, and signal levels. For a parallel port, there will be many signal pins, and cable 50 will comprises a number of conductors. A recently proposed parallel port specification is the I.E.E.E. P-1284 D2.00 (Sep. 10, 1993) standard, a Centronics parallel-compatible port. This specification is expected to be adopted by computer and workstation manufacturers.
Tables 1, 2 and 3 below set forth pin-outs and other information for the 1284-A, 1284-B and 1284-C connector pin assignments under this proposed standard. In these tables, "Bi-Di" denotes that the bi-directional data signals can be read by some, but not all, host devices, "H" denotes the host, and "P" denotes the peripheral device. Notation such as "nAck" means that the "ACKNOWLEDGE" signal is active when low, or "0". The "Compatible" and "ECP" columns refer to the compatible per se and the extended capability port modes of a 1284-compliant parallel port. The present invention is directed to the "Compatible" mode, but other modes are also possible.
Typically the parallel port signals from host 10 are provided by an integrated circuit ("IC"), such as IC 100 in FIG. 1. One such product is the so-called NEC super-I/O IC that provides two serial output ports, a floppy disk controller, an IDE drive interface, and a mode-selectable parallel port. Programming a particular mode into such an IC, e.g., via CPU 20, can select (among other functions) the mode of operation of parallel port 40. Thus, port 40 can be software-operated as a 1284-compliant compatible port, or other Centronics parallel-compatible port. Suitable mode-control software may be stored in memory 30, as shown in FIG. 1.
TABLE 1 ______________________________________ 1284-A Connector Pin Assignment Pin # Source Compatible ECP ______________________________________ 1 H nStrobe Host Clk 2 Bi-Di Data 1 (Least Significant Bit) 3 Bi-Di Data 2 4 Bi-Di Data 3 5 Bi-Di Data 4 6 Bi-Di Data 5 7 Bi-Di Data 6 8 Bi-Di Data 7 9 Bi-Di Data 8 (Most Significant Bit) 10 P Nack Peripheral Clock 11 P Busy Peripheral Ack 12 P PError nAckReverse 13 P Select Xflag 14 H nAutoFd HostAck 15 P nFault nPeriphRequest 16 H nInit nReverseRequest 17 H nSelectIn 1284 Active 18 Sig'l Gnd (Nstrobe) 19 Sig'l Gnd (Data 1 and Data 2) 20 Sig'l Gnd (Data 3 and Data 4) 21 Sig'l Gnd (Data 5 and Data 6) 22 Sig'l Gnd (Data 7 and Data 8) 23 Sig'l Gnd (Busy and Nfault) 24 Sig'l Gnd (Perror, Select, & Nack) 25 Sig'l Gnd (Nautofd, Nselectin, & Ninit) ______________________________________
Connector 80 will be a 25 pin subminiature D-shell type connector when the host output parallel port 40 follows a 1284-A connector pin assignment. By contrast, connector will be a miniature 36 pin ribbon type connector when host output parallel port 40 follows a 1284-B or 1284-C connector pin assignment.
Table 1 is also applicable to other Centronics parallel-compatible ports if it is recognized that pins 2-9 are then unidirectional output only signals driven by the host, and that pins 18-25 are then ground pins.
TABLE 2 ______________________________________ 1284-B Connector Pin Assignment Pin # Source Compatible ECP ______________________________________ 1 H Nstrobe HostClk 2 Bi-Di Data 1 (Least Significant Bit) 3 Bi-Di Data 2 4 Bi-Di Data 3 5 Bi-Di Data 4 6 Bi-Di Data 5 7 Bi-Di Data 6 8 Bi-Di Data 7 9 Bi-Di Data 8 (Most Significant Bit) 10 P Nack PeriphClk 11 P Busy PeriphAck 12 P Perror Nackreverse 13 P Select Xflag 14 H Nautofd HostAck 15 Not Defined 16 Logic Gnd 17 Chassis Gnd 18 P Peripheral Logic High 19 Sig'l Gnd (Nstrobe) 20 Sig'l Gnd (Data 1) 21 Sig'l Gnd (Data 2) 22 Sig'l Gnd (Data 3) 23 Sig'l Gnd (Data 4) 24 Sig'l Gnd (Data 5) 25 Sig'l Gnd (Data 6) 26 Sig'l Gnd (Data 7) 27 Sig'l Gnd (Data 8) 28 Sig'l Gnd (Perror, Select, Nack) 29 Sig'l Gnd (Busy, Fault) 30 Sig'l Gnd (Nautofd, Nselectin, Ninit) 31 H Ninit Nreverserequest 32 P Nfault Nperiphrequest 33 Not Defined 34 Not Defined 35 Not Defined 36 H Nselectin 1284 Active ______________________________________
TABLE 3 ______________________________________ 1284-C Connector Pin Assignment Pin # Source Compatible ECP ______________________________________ 1 P Busy PeriphAck 2 P Select Xflag 3 P Nack PeriphClk 4 P Nfault Nperiphrequest 5 P Perror Nackreverse 6 Bi-Di Data 1 (Least Significant Bit) 7 Bi-Di Data 2 8 Bi-Di Data 3 9 Bi-Di Data 4 10 Bi-Di Data 5 11 Bi-Di Data 6 12 Bi-Di Data 7 13 Bi-Di Data 8 (Most Significant Bit) 14 H Ninit Nreverserequest 15 H Nstrobe HostClk 16 H Nselectin 1284 Active 17 H Nautofd HostAck 18 H Host Logic High 19 Signal Ground (Busy) 20 Signal Ground (Select) 21 Signal Ground (Nack) 22 Signal Ground (nfault) 23 Signal Ground (PError) 24 Signal Ground (Data 1) 25 Signal Ground (Data 2) 26 Signal Ground (Data 3) 27 Signal Ground (Data 4) 28 Signal Ground (Data 5) 29 Signal Ground (Data 6) 30 Signal Ground (Data 7) 31 Signal Ground (Data 8) 32 Signal Ground (nInit) 33 Signal Ground (nStrobe) 34 Signal Ground (nSelectIn) 35 Signal Ground (nAutoFd) 36 P Peripheral Logic High ______________________________________
One problem with testing parallel ports, whether defined by the P-1284 D2.00 standard or by another standard, is that active test equipment must be used. By "active" it is meant that the port-testing equipment requires an external power supply, typically a power supply that operates from 110/220 VAC. Providing this power can require re-wiring the test chamber in which the host equipment is to be tested.
Further, when temperature testing the host equipment, a sufficiently large test oven must be provided to accommodate the additional bulk and wiring associated with the parallel port test equipment. Modern host test facilities are automated, with the host equipment being handled robotically at the test station. But the necessity to couple wires, equipment, and an AC-generated power supply for testing a host parallel port is cumbersome, expensive, and slows the automated test process.
Thus, there is a need for a method and apparatus for testing a software-controllable parallel port without using bulky test equipment. Preferably such testing should occur using a small, passively operated, stand-alone device. The present invention discloses such a method and test device.